The PCI bus is a high-performance expansion bus architecture that was designed to replace the traditional ISA bus(Industry Standard Architecture bus)and EISA bus (Extended industry Standard Architecture bus) buses found in many X86 based personal computers. A group of companies (including Intel, IBM, Compaq, DEC, Dell, NEC, etc.) cooperated in preparing and publishing a standard specification for the PCI bus. The specifications for the PCI bus is available from the PCI Special Interest Group, 5200 Elam Young Parkway, Hillsboro, Oreg.
In order to expand the capacity of a standard PCI bus, a bus bridge termed a PCI to PCI bridge is used. A PCI bridge provides a connection path between two independent PCI busses. The primary function of a PCI to PCI bridge is to allow transactions to occur between a master on one PCI bus and a target on the other PCI bus. A PCI to PCI bridge provides system and option card designers with the ability to overcome electrical loading limits inherent in a standard PCI bus. A PCI Special Interest Group has developed and published a specification for PCI to PCI Bridges (PCI to PCI Bridge Architecture Specifications Rev. 1.0 Apr. 5, 1994). A number of merchant semiconductor companies, such as Digital Equipment Corporation, market PCI bridge circuits. That is such companies market integrated circuits that conform to the PCI to PCI bridge specifications. For example see the 21050 PCI to PCI Bridge marketed by Digital Equipment Corporation.
The PCI to PCI bridge specification defines a number of terms which will be used hereinafter. The terms and their definition are:
initiating bus--the master of a transaction that crosses a PCI to PCI bridge is said to reside on the initiating bus. PA1 target bus--the target of a transaction that crosses a PCI to PCI bridge is said to reside on the target bus. PA1 primary interface--the PCI interface of the PCI to PCI bridge that is connected to the PCI bus closest to the CPU is referred to as the primary PCI interface. PA1 secondary interface--the PCI interface of the PCI to PCI bridge that is connected to the PCI bus farthest from the CPU is referred to as the secondary PCI interface. PA1 downstream--transactions that are forwarded from the primary interface to secondary interface of a PCI to PCI bridge are said to be flowing downstream. PA1 upstream--transactions that are forwarded from the secondary interface to primary interface of a PCI to PCI bridge are said to be flowing upstream.
A PCI to PCI bridge has two PCI interfaces, a primary interface and a secondary interface. As defined by the PCI bridge specification, each of the interfaces is capable of either master or target operation. With respect to the bus which initiates an operation, the bridge functions as a target on behalf of the target that actually resides on the target bus. Likewise, with respect to the target bus, the bridge functions as a master on behalf of the master that actually resides on the initiating bus.
FIG. 1 shows a typical system that includes a PCI to PCI bridge of the type defined by the "PCI Special Interest Group". A CPU 110 has a host bus 111 which connects to a DRAM memory 112 and host bridge 115. The host bridge 115 connects PCI Bus 0 to the Host Bus 111. A number of PCI bus master devices 120-A, 120-B and 120-C are connected to the PCI Bus 0. A PCI to PCI bridge 130 is used to expand the bus capacity. With respect to PCI bus 0, PCI bridge 130 acts like any other PCI bus master device. However, PCI bridge 130 is also connected to a second PCI bus "PCI BUS 1" which has PCI bus master Devices 121-D, 121-E and 121-F connected thereto. With respect to PCI Bus 1, PCI-PCI bridge 130 acts similar to any other PCI bus master device.
Data can pass through PCI to PCI bridge 130 in either direction. That is, data can pass from a device on PCI BUS 0 to a device on PCI BUS 1 or data can pass in the opposite direction from a device on PCI 1US I to a device on PCI BUS 0. In a situation where several devices are trying to send data in different directions through the bridge 130, it is desirable that the direction of transmission through the bridge alternate. However, in some situations a condition known as "livelock" may occur. When "livelock" occurs the bridge continues to service the devices sending data through the bridge in one direction and the devices trying to send data through the bridge in the other direction are "locked" out from transmitting data through the bridge. The present invention is directed to preventing "livelock" from occurring.
FIG. 2 shows the general structure of a prior art PCI to PCI bridge such as the PCI to PCI bridge marketed by Digital Equipment Corporation under the designation "DECchip 21050". The PCI to PCI bridge has a primary interface 201 and a secondary interface 202. Each of the interfaces has a data path and a control path. The data paths include buffers 210 and 211. The control path in turn has two branches. One branch of the control path includes a Primary Target Interface 221 and a Secondary Master Interface 222. The second branch of the control path includes a Primary Master Interface 223 and a Secondary Target Interface 224. Configuration registers 230 include standard PCI registers such as the Vendor ID Register, the Device ID Register, the Command Register, timers, Memory Base and Limit Registers and other control circuits. The configuration registers control the operation of the PCI bus and they are set and perform the functions specified in the PCI bus standard.